I note that in the technical overview it stated that issues with this had been found on Linux because of the use of a light implementation of TCP/IP. We are considering implementing this on a new board but would require it to be robust, so wonder what the status is now?
Is it robust and are people using it from Linux?
Thank you,
Dave
Hello Dave,
This is not a function that we are using every day but according to Stefan Haas, the connection between a Linux PC and the IPMC should work. Please let us know if you are experiencing any problems.
Cheers,
Markus
Hi Markus,
Our question was higher level than that, being do we connect the JTAG Master from the IPMC where the use case would be running xvc, but our concern was the comments from Julian, I guess being that the IPMC uses lwIP.
As our FPGA is Versal Premium I note on digging today that Xilinx support xvc on the Versal itself https://docs.xilinx.com/r/en-US/ug908-vivado-programming-debugging/Xilinx-Virtual-Cable-XVC-Flow-for-Versal-Devices where there is then no concern about cut down network stack, so for us this is clearly the way to go.
Thank you,
Dave
Hello Dave,
it depends what you are trying to achieve, this is not clear to me. The virtual cable server on the SoC works very well, we have been using this for year on the MUCTPI. However, it only runs once the SoC has booted and is running the OS.
It does not work if you want to use it to debug boot issues or boot the SoC via JTAG during the development. In this case the IPMC JTAG master is useful, in particular if you have several boards in a shelf. I would recommend to implement some logic which allows connecting the SoC/Versal JTAG pins to either a USB-UART interface (useful during debugging in the lab) or the IPMC JTAG master (useful in the experiment). This is what we implemented on the MUCTPI.
cheers,
Stefan