Dear Ralf,
Thanks for your support on the SoC development of L0Muon Endcap phase-II upgrade.
I have a question about the CERN-IPMC’s specification especially in the hardware parts.
Could you confirm the GPIO, USERIO0-34 and IPMIO0-15, can handle tri-state? As far as I read the example source code, it looks supported well. However, I could not find any description in the documentations explicitly [1]. I would confirm this just in case.
I heard that Julian, the hardware expert, was left. I would appreciate if this question is forwarded to the current experts.
We are now newly adding one connection from the GPIO to the U20 EN1 (pin
- net directly to toggle the H/L with keeping the SW5.
If the pin handle tri-state, there should not be problem.
Thanks in advance.
Best regards,
Shota
[1] CERN-IPMC
Hi Shota,
Thanks for your message.
I am not sure I will be able to answer. Since this is about hardware I am adding Stefan to the conversation, and since it might be of interest to the larger community, I am adding the CERN IPMC discourse forum where the conversation will appear. I hope you don't mind. I am sure we will find you the right answers.
Cheers,
Ralf.
Hi Ralf,
Thank you for forwarding this message.
There are no problem in putting this in the discourse. I keep watching that thread on the Discourse.
Best regards,
Shota
Hello Shota,
yes, the USER and IPM I/Os pins can be tri-stated. Do you want to use the IPMC pin to reset the SoC? I this case you can simply connect the Payload reset# pin of the IPMC (pin 223) to your reset chip input. This output from the IPMC is tri-stated when the IPMC de-assert the payload reset.
cheers,
Stefan
Hello Stefan,
Thank you for your confirmation.
The use of that IPMC pin is to reset the SoC. We are now routing the reset signals to the two reset pins individually, MPSoC power-on reset and MPSoC system reset. To realize the individual behavior, two GPIO pins are used.
I am not sure how this payload-reset# bin (223) can be toggled. Even I read the documents, I could not find the description of behavior.
Is this pin can be toggled via the IPMC software API?
Best,
Shota
Hello Shota,
please see below:
I am not sure how this payload-reset# bin (223) can be toggled. Even I
read the documents, I could not find the description of behavior.
Is this pin can be toggled via the IPMC software API?
This is the standard signal used to reset the payload. It is automatically asserted as part of the payload activate/deactivate sequence. You can also force a payload reset using shelf manager command line interface command "boardreset". You can also use an ipmitool command:
ipmitool -I lan -U '' -P '' -H <ipmc-ipaddr> picmg frucontrol 0 0
If you want to be able to toggle the PS_SRST input as well, you should connect a free IPMC GPIO pin to the corresponding input of the reset chip. You will then have to implement an OEM command to issue this type of reset.
Below is a snippet of code which shows how to pulse the reset signal, assuming you are using the USER I/O pin 10, but you can use any unused USER or IPM I/O pin:
signal_t srst_sig = USER_IO_10;
// assert reset: drive output pin low
signal_set_pin(&srst_sig, SIGNAL_LOW);
// wait 100 us
udelay(100);
// de-assert reset: set output to high impedance signal_set_pin(&srst_sig, SIGNAL_HIGHZ);
Let me know if you have any further questions.
cheers,
Stefan
Hello Stefan,
Thank you very much for clarification and examples.
I will consider the use case and decide the pins.
Best regards,
Shota
Dear Shota, dear Stefan,
Thanks a lot for the successful exchange of information.
I am only writing because I made a mistake when adding the address for this exchange to appear on Discourse. It should have been epesebe-xtca-support@cern.ch from the beginning.
I have corrected the address and the exchange also appears in the Discourse for future reference: https://cern-ipmc-forum.web.cern.ch/t/specification-of-the-cern-ipmcs-gpio-pins
Sorry for the inconvenience. I hope that now we can follow by email and have a trace in Discourse.
Cheers,
Ralf.
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