Re: [Re] Management of non-intelligent RTM

Hello Fatih,

thank you, this is exactly what I needed. However I would also need the I2C address of the EEPROM and the offset where you want to store the RTM FRU data. I will already prepare the necessary #define statements.

BTW, do you already have the RTM in hand?

cheers,

Stefan

Hi Stefan,

Here are the I2C address of the EEPROMs intended for the RTM :

  • On RTM (via IPMB-L) : Address = 0x50 - Offset = 0x0
  • On LATOURNETT blade (via MGT I2C) : Address = 0x51 - Offset = 0x0

No, we don’t have the non-intelligent RTM yet.

Cheers,

Fatih

Hello Fatih,

below are the #define statements adapted to the hardware description of your RTM, to be included in the user_def.h file of your project:

/*
Author: Stefan Haas, CERN
Description: Example for defines required for a non-intelligent RTM
*/

#define CFG_RTM_FRU_ENABLE

#define CFG_RTM_PRESENCE_SIGNAL {
i2c_addr: 0x42,
pin: PCA9555(15),
active: SIGNAL_LOW,
inactive: SIGNAL_HIGH
}
#define CFG_RTM_I2C_BUFFER_ENABLE_SIGNAL {
i2c_addr: 0x44,
pin: PCA9555(0),
active: SIGNAL_HIGH,
inactive: SIGNAL_LOW
}
#define CFG_RTM_I2C_BUFFER_READY_SIGNAL { pin: PIN_INVALID }
#define CFG_RTM_I2C_RESET_SIGNAL { pin: PIN_INVALID }
#define CFG_RTM_MP_ENABLE_SIGNAL {
i2c_addr: 0x44,
pin: PCA9555(1),
active: SIGNAL_HIGH,
inactive: SIGNAL_LOW
}
#define CFG_RTM_MP_GOOD_SIGNAL {
i2c_addr: 0x44,
pin: PCA9555(3),
active: SIGNAL_HIGH,
inactive: SIGNAL_LOW
}
#define CFG_RTM_PAYLOAD_RESET_SIGNAL { pin: PIN_INVALID }

// RTM hot-swap switch
#define CFG_RTM_HANDLE_SWITCH_SIGNAL IPM_IO_2_ACTL

// RTM payload power sequence
#define RTM_PWR_ENABLE_SIGNAL {
i2c_addr: 0x44,
pin: PCA9555(2),
active: SIGNAL_HIGH,
inactive: SIGNAL_LOW
}
#define RTM_PWR_GOOD_SIGNAL {
i2c_addr: 0x44,
pin: PCA9555(4),
active: SIGNAL_HIGH,
inactive: SIGNAL_LOW
}
#define CFG_RTM_PAYLOAD_POWER_ON_SEQ
PSQ_ENABLE_SIGNAL(RTM_PWR_ENABLE_SIGNAL),
PSQ_END
#define CFG_RTM_PAYLOAD_POWER_OFF_SEQ
PSQ_DISABLE_SIGNAL(RTM_PWR_ENABLE_SIGNAL),
PSQ_END

// RTM LEDs
#define CFG_RTM_FRU_LED_COUNT 2 /* excluding the blue LED */
#define CFG_RTM_FRU_LED_COLORS LED_CAP_RED, LED_CAP_GREEN
#define CFG_RTM_FRU_LED_DEFAULT_COLORS LED_LC_RED | LED_OVR_RED | LED_LC_GREEN | LED_OVR_GREEN
#define CFG_RTM_BLUE_LED_SIGNAL USER_IO_27_ACTL
#define CFG_RTM_FRU_LED_SIGNALS {
{ USER_IO_28_ACTL, USER_IO_29_ACTL }
}

// RTM FRU EEPROM on the front blade
#define CFG_RTM_FRU_INFO_EEPROM_SIZE 64
#define CFG_RTM_FRU_INFO_EEPROM_ADDR 0x2a2
#define CFG_RTM_FRU_INFO_EEPROM_OFFSET 0

#define CFG_RTM_STABLE_POWER 10000 /* 10 W /
#define CFG_RTM_PAYLOAD_RESET_DELAY 50 /
50 ms */

In addition, you need to put a file with the RTM FRU information called rtm-fru-info.inf (see below) in the ipmc-user folder. You can edit this file to adapt the FRU contents to your requirements:

[Common Header]
Version = 1

[Board Info]
Version = 1
Language Code = en
Mfg Date/Time = 01/03/2025
Manufacturer = LAPP
Product Name = LATOURNETT RTM
Serial Number = RTM0000001
Part Number = A
FRU Programmer File ID = rtm-fru-info.inf

[Product Info]
Version = 1
Language Code = en
Manufacturer = LAPP
Product Name = LATOURNETT RTM
Part/Model Number = 000001
Product Version = Rev 1.0
Serial Number = RTM0000001
Asset Tag =
FRU File ID = rtm-fru-info.inf

[LED description]
0 = ‘HS;; The BLUE LED’
1 = ‘OOS;; Out-of-service LED’
2 = ‘IS;; In-service LED’

The firmware compiles, but we can unfortunately not test the RTM functionality, since we do not have any ATCA blade with a non-intelligent RTM at our disposal.

Please let me know if you have any issues.

cheers,

Stefan

Hi Stefan,

Thank you for everything.
We’ll be in touch if we have any further questions.

Cheers,

Fatih