so far nobody has requested the use of external interrupts. Although the IPMC does of course use interrupts internally, I’m afraid there are no interrupt capable pins available on the mezzanine connector of the IPMC.
I would check the input signal one per main loop, there is a callback function for that. You will of course not get a quick response time then. May I ask what signal you are monitoring and why you need a “fast” response time (BTW, how fast is fast enough?)
just to be clear: you want to simply assert/de-assert a user I/O pin when the board is powering up or down? This can be done easily by defining a custom power sequence, see here:
Hi Stefan,
We were hoping that we could send an existing signal to a user IO pin as well. The reason for this is that the FPGA on the LASP board has a power down sequence procedure setup to NOT stress the FPGA. The signal John was talking about is the -48V fault signal that has hold-up CAPs to maintain the +12V rails for long enough to allow a clean power down sequence for the IPMC which could work as well for the FPGA. Could you interrupt to call some user code to run when this happens? This could also happen if someone attempted to extract the LASP board, but forgot to properly shutting down the LASP FPGA.
thank you for the clarification. Unfortunately the user I/O pins do not support interrupts, so this is not an option here. I also believe that events that require a very fast reaction times are best handled in hardware. On the other hand over-temperature conditions for example can be handled by the IPMC, given that temperature typically does not change that fast.
Sorry for the late reply. Basically, we’re interested in getting potential fault conditions on usr pins with faster response than implied by the polling loop. It’s not a critical requirement, but this came up in a recent discussion about potential problems and how to handle them.