Hi,
Information regarding the CERN-IPMC JTAG Master:
in the document “CERN-IPMC - Pinout and mapping”, is pin 109 “JTAG Master - TDO out” connected to the TDI pin of an FPGA ?
if this is correct, pin 109 should have the name “JTAG Master - TDI out” like on a JTAG Header Programmer
Information regarding the CERN-IPMC JTAG Slave:
in the document “CERN-IPMC - Pinout and mapping”, is pin 112 “JTAG input - TDO” rather an output ?
because the document “CERN-IPMC - hardware guide” figure 7 (JTAG slave interface connectivity), it is indicated that pin 112 is connected to pin 3 (input) of the FlashPro4 Programmer.
note: the direction of the TDI & TDO arrows are reversed
concerning the IPMC JTAG master, the TDO pin 109 is indeed an output and should be connected to the TDI of an FPGA, i.e. the TDO pin should be connected to the TDI pin of the next device in the JTAG chain and vice versa. We will update the hardware documentation to clarify this better.
Concerning the JTAG slave interface of the IPMC which goes to the SoC/FPGA on the mezzanine, there is indeed a mistake in the documentation, the arrows for the TDI and TDO signals point the wrong way in the drawing, thanks for pointing this out. The connections are however correct as shown. I agree that the naming is also misleading, the pin names should have been called JTAG slave and not JTAG input. We will update the document.
I realized that there was a mistake in figure 7 showing the connection between the FlashPro connector and the IPMC: the TRST pin from the connector should not be connected to the IPMC. This is because the IPMC pin 223 (PayloadReset#) is actually an open-drain output that is intended to reset the payload circuitry of the blade. In an early revision of the IPMC mezzanine, pin 223 was indeed also connected to the TRST input of the SoC/FPGA on the mezzanine by mistake, but this is not the the case for the current revisions (V3 and V4). In any case, the TRST input is not required at all to program the IPMC.
The documentation has been updated accordingly and I have also added some additional clarifications concerning the JTAG master interface:
yes, if you are planning on using that signal to reset the payload, it’s best to add a pull-up resistor on the board. It would be possible to make the PayloadReset# signal a push-pull output in the firmware, however it was kept as an open drain for compatibility with older ATCA blade designs that pulled this signal low externally (e.g. from a reset supervisor chip).