IPMC JTAG Virtual Cable

We have observed that the JTAG virtual cable server is reliable and works well. We also noted that the data rate over the JTAG chain is fixed at 10MHz. The Xilinx programming software provides an option for users to set the desired frequency and the IPMC XVC server responds to this command, but the clock frequency never changes.

For imperfect signal environments, where signal integrity may involve compromises, it would be beneficial to allow users to slow down the JTAG programming chain to avoid marginal behavior while programming at 10MHz.

Dear @jameel,

Thank you for the feedback. You’re right that the XVC protocol allows changing the clock frequency but, unfortunately, we had to fix it by design. As we are really limited in the resource we have on the FPGA side, it was not possible to implement a configurable clock divider.

Do you face an issue with the clock frequency which is too high? I guess 10MHz is still slow enough to not have too much constraint on it.

Best regards,